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| 32C408B 4 Megabit (512K x 8-Bit) SRAM A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 A4 CS I/O1 I/O2 Vcc Vss I/O3 I/O4 WE A5 A6 A7 A8 A9 1 36 NC A18 A17 A16 A15 OE I/O8 I/O7 ROW DECODER MEMORY MATRIX 1024 ROWS x 4096 COLUMNS DQ0 32C408B Vss Vcc I/O6 I/O5 A14 A13 A12 A11 A10 CS DQ7 COLUMN I/O INPUT DATA CONTROL COLUMN DECODER A18 A17 A16 A15 A14 A3 A2 A1 A0 DQ0 Memory WE OE DQ7 18 19 NC Logic Diagram FEATURES: * 512k x 8-bit CMOS architecture * RAD-PAK(R) technology hardened against natural space radiation * Total dose hardness: - > 100 krad (Si), depending upon space mission * Single event effect: - SELTH: > 68 MeV/mg/cm2 - SEUTH: < 3MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit * Package: -36 pin RAD-PAK(R) flat pack * Fast propagation time: -20, 25, 30 ns maximum access time * Single 5V + 10% power supply * Low power dissipation: - Standby: 60mA (TTL); 10mA (CMOS) - Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30 ns) * TTL compatible inputs and outputs * Fully static operation - No clock or refresh required * Three state outputs DESCRIPTION: Maxwell Technologies' 32C408B high-speed 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using RAD-PAK(R) packaging technology, the 32C408B realizes higher density, higher performance and lower power consumption, and is well suited for high-speed system application. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 32C408B is equipped with eight common input/ output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. Maxwell Technologies' patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. In a GEO orbit, RAD-PAK can provides true greater than 100 krad (Si) total radiation dose tolerance; dependent upon space mission. The patented radiation-hardened RAD-PAK technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with packaging and screening up to Class S. 05.02.02 Rev 7 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM TABLE 1. 32C408B ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Storage Temperature Operating Temperature SYMBOL VIN, VOUT VCC PD TS TA MIN -0.5 -0.5 --65 -55 32C408B MAX VCC+0.5 7.0 1.0 +150 +125 UNIT V V W C C TABLE 2. 32C408B RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Ground Input High Voltage 1 Input Low Voltage 2 Thermal Impedance 1. VIH(max) = VCC + 2.0V ac(pulse width < 10ns) for I < 20mA. 2. VIL (min) = -2.0V ac(pulse width < 10ns) for I < 20mA. SYMBOL VCC VSS VIH VIL MIN 4.5 0 2.2 -0.5 -MAX 5.5 0 VCC+0.5 0.8 0.63 UNIT V V V V C/W Memory JC TABLE 3. 32C408B DC ELECTRICAL CHARACTERISTICS (VCC=5V +/- 10%, TA = -55 TO +1`25C, UNLESS OTERWISE SPECIFIED PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage CONDITION VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL, VOUT =VSS to VCC IOL = 8mA IOH = -4mA SYMBOL ILI ILO VOL VOH ICC SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ---ISB ISB1 CIN CI/O 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 --------MIN -2 -2 -2.4 -180 170 160 60 10 7 8 pF pF mA TYP ---MAX 2 2 0.4 -UNIT A A V V mA Average Operating Cur- Min cycle, 100% Duty, CS=VIL, IOUT=0mA, VIN = VIH or VIL rent -20 -25 -30 Standby Power Supply Current Input Capacitance1 Output 1. Guaranteed by Design Capacitance1 CS = VIH f = 0MHz, CS > VCC - 02V, VIN > VCC - 0.2V or VIN < 0.2V VIN = 0V, f = 1MHz, TA = 25 C. VI/O = 0V 05.02.02 Rev 7 All data sheets are subject to change without notice 2 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM TABLE 4. 32C408B AC CHARACTERISTICS FOR READ CYCLE (VCC=5V +/- 10%, TA = -55 TO +1`25C, UNLESS OTERWISE SPECIFIED PARAMETER Read Cycle Time -20 -25 -30 Address Access Time -20 -25 -30 Chip Select Access Time -20 -25 -30 Output Enable to Output Valid -20 -25 -30 Chip Select to Output in Low-Z -20 -25 -30 Output Enable to Output in Low-Z -20 -25 -30 Chip Deselect to Output in High-Z -20 -25 -30 Output Disable to Output in High-Z -20 -25 -30 Output Hold from Address Change -20 -25 -30 Chip Select to Power Up Time -20 -25 -30 Chip Select to Power Down Time -20 -25 -30 SYMBOL tRC SUBGROUPS 9, 10, 11 20 25 30 tAA 9, 10, 11 ---tCO 9, 10, 11 ---tOE 9, 10, 11 ---tLZ 9, 10, 11 ---tOLZ 9, 10, 11 ---tHZ 9, 10, 11 ---tOHZ 9, 10, 11 ---tOH 9, 10, 11 3 5 5 tPU 9, 10, 11 ---tPD 9, 10, 11 ---10 15 20 0 0 0 ---5 6 8 5 6 8 0 0 0 3 3 3 ------------MIN TYP 32C408B MAX ---ns 20 25 30 ns 20 25 30 10 12 14 ---ns ---ns ---ns ---ns ---ns ---ns ---ns UNIT ns Memory ns 05.02.02 Rev 7 All data sheets are subject to change without notice 3 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM TABLE 5. 32408B FUNCTIONAL DESCRIPTION 1 CS H L L L 1. X = don't care. WE X H H L OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN 32C408B SUPPLY CURRENT ISB, ISB1 ICC ICC ICC TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE (VCC=5V +/- 10%, TA = -55 TO +1`25C, UNLESS OTERWISE SPECIFIED PARAMETER Write Cycle Time -20 -25 -30 Chip Select to End of Write -20 -25 -30 Address Setup Time -20 -25 -30 Address Valid to End of Write -20 -25 -30 Write Pulse Width (OE High) -20 -25 -30 Write Recovery Time -20 -25 -30 Write to Output in High-Z -20 -25 -30 SYMBOL tWC SUBGROUPS 9, 10, 11 20 25 30 tCW 9, 10, 11 14 15 17 tAS 9, 10, 11 0 0 0 tAW 9, 10, 11 14 15 17 tWP 9, 10, 11 14 15 17 tWR 9, 10, 11 0 0 0 tWHZ 9, 10, 11 ---5 5 6 ---------ns ------ns ------ns ------ns ------ns ------ns MIN TYP MAX UNIT ns Memory 05.02.02 Rev 7 All data sheets are subject to change without notice 4 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE (VCC=5V +/- 10%, TA = -55 TO +1`25C, UNLESS OTERWISE SPECIFIED PARAMETER Write Pulse Width(OE Low) -20 -25 -30 Data to Write Time Overlap -20 -25 -30 End Write to Output Low-Z 1 -20 -25 -30 Data Hold from Write Time -20 -25 -30 SYMBOL tWP1 SUBGROUPS 9, 10, 11 ---tDW 9, 10, 11 9 10 11 tOW 9, 10, 11 ---tDH 9, 10, 11 0 0 0 ---6 7 8 ---20 25 30 MIN TYP 32C408B MAX ---ns ---ns ---ns ---UNIT ns Memory FIGURE 1. TIMING WAVEFORM OF WRITE CYCLE(1) (OE CLOCK) 05.02.02 Rev 7 All data sheets are subject to change without notice 5 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED) 32C408B 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high or WE going high. tWP is measured from beginning of write to end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10.When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. Memory FIGURE 3. TIMING WAVEFORM OF READ CYCLE(1) (ADDRESS CONTROLLED, CS = OE = VIL, WE = VIH) 05.02.02 Rev 7 All data sheets are subject to change without notice 6 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM FIGURE 4. TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) 32C408B 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. Memory 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device. 5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention is necessary during read and write cycle. FIGURE 5. SRAM HEAVY ION CROSS SECTION 05.02.02 Rev 7 All data sheets are subject to change without notice 7 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM 32C408B FIGURE 6. SRAM PROTON SEU CROSS SECTION STATIC Memory 05.02.02 Rev 7 All data sheets are subject to change without notice 8 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM 32C408B Memory 36 PIN FLAT RAD-PAK(R) PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N F36-01 Note: All dimensions in inches 0.390 0.088 0.005 0.122 0.015 0.008 -0.638 -0.560 0.005 DIMENSION NOM 0.135 0.017 0.010 0.930 0.645 -0.565 0.040 0.050 BSC 0.400 0.098 0.032 36 0.410 0.108 -MAX 0.148 0.019 0.012 0.940 0.652 0.690 --- 05.02.02 Rev 7 All data sheets are subject to change without notice 9 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM Important Notice: 32C408B These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts. Memory 05.02.02 Rev 7 All data sheets are subject to change without notice 10 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) SRAM Product Ordering Options Model Number 32C408B XX F X -XX Feature Access Time 32C408B Option Details 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25C) I = Industrial (testing @ -55C, +25C, +125C) Memory Package F = Flat Pack Radiation Feature RP = RAD-PAK(R) package Base Product Nomenclature CMOS 512kword x 8-bit Static RAM 05.02.02 Rev 7 All data sheets are subject to change without notice 11 (c)2002 Maxwell Technologies All rights reserved. |
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